Qiaoyan Yu

Qiaoyan Yu

Associate Professor

Education

  • B.S. Xidian University, P.R. China, 2002
  • M.S. Zhejiang University, P.R. China, 2005
  • Ph.D. University of Rochester, NY, 2011

Biography

I am an associate professor at the University of New Hampshire. I received a B.S. degree in Communication Engineering from Xidian University of China in July 2002. Two and a half years later, I obtained a M.S. degree in Communication and Information Engineering from Zhejiang University of China. I received a M.S. and Ph.D. degree in Electrical and Computer Engineering from the University of Rochester in 2007 and 2011, respectively. I am a member of the IEEE, the IEEE Circuit and System Society, and ACM.

Research Areas

My research interests includes error control for networks-on-chip, fault-tolerance for many-core systems, and emerging nanoelectronics. More specifically, I am working on

  • Error Modeling for System Components in Emerging Technologies
  • Transient and Permanent Error Management for Processing Core, Interconnect Links
  • Adaptive Error Control Methodology for Hybrid Multi-Core Systems
  • Reliable Integrated Circuits for Medical and Aerospace Applications

Publications

Book chapter and book

  • P. Ampadu, B. Fu, D. Wolpert and Q. Yu, “Adaptive voltage control for energy-efficient NoC links,” in Low-Power Networks on Chip, C. Silvano, M. Lajolo, G. Palermo, Ed. Milan: Springer Press, 2011, pp. 45-69.
  • Q. Yu and P. Ampadu, “Transient and permanent error control for Networks-on-Chip,” Springer Press, 2011.

Journal Articles

  • Q. Yu and P. Ampadu, “Dual-layer cooperative error control coding for transient errors in NoCs,” IEEE Trans. on Very Large Scale Integr. (VLSI) Syst. (in press).
  • Q. Yu and P. Ampadu, “A dual-Layer method for transient and permanent error co-management in NoC links,” IEEE Trans. on Circuit and Systems II-Express Briefs, vol. 58, no. 1, pp. 36-40, Jan. 2011.
  • Q. Yu and P. Ampadu, “A flexible parallel simulator for networks-on-chip with error control,” IEEE Trans. on Computer-Aided Design of Integr. Circuits and Syst. (TCAD), vol. 29, no. 1, pp.103-116, Jan. 2010.
  • Q. Yu and P. Ampadu, “Adaptive error control for nanometer scale NoC links,” IET Computers & Digital Techniques-Special Issue on Advances in Nanoelectronics Circuits and Syst., vol. 3, no. 6, pp. 643-659, Nov. 2009.
  • D. Huo, Q. Yu, D. Wolpert and P. Ampadu, “A simulator for ballistic nanostructures in a 2-D electron gas,” ACM J. on Emerging Technologies in Computing Syst. (JETC), vol. 5, no. 1, Article 5, Jan. 2009.
  • J. Chen. P. Liu, Q. Yao, C. Shi, D. Zheng, Q. Yu and L. Lai, “MD16: 16-bit DSP processor with special RISC philosophy,” J. Circuits and Systems, vol. 12, no. 5, pp. 65-71,145, Oct. 2007.
  • Q. Yu, P. Liu and Q. Yao, “Data hazard detection method for DSP with heavily compressed instruction set,” J. Zhejiang University(Engineering Science), vol. 39, no. 10, pp.1501-1506, Oct. 2005.

Conference Articles

  • Q. Yu, M. Zhang and P. Ampadu, “Exploiting inherent information redundancy to manage transient errors in NoC routing arbitration,” in Proc. 5th ACM/IEEE Intl. Symp. on Networks-on-Chip (NoCS’11), pp. 105-112, May 2011.
  • Q. Yu and P. Ampadu, “Transient and permanent error co-management method for reliable networks-on-chip,” in Proc. 4th ACM/IEEE Intl. Symp. on Networks-on-Chip (NoCS’10), pp. 145-154, May 2010.
  • Q. Yu, B. Zhang, Y. Li and P. Ampadu, “Error control integration scheme for reliable NoC,” in Proc. 2010 IEEE Intl. Symp. on Circuit and Syst. (ISCAS’10), pp. 3893-3896, May 2010.
  • Q. Yu and P. Ampadu, “Dual-layer cooperative error control for a reliable nanoscale NoC,” in Proc. 24th IEEE Intl. Symp. on Defect and Fault Tolerance in VLSI Sys. (DFT’09), pp. 431-439, Oct. 2009.
  • V. Kaushal, M. Margala, G. Guarino, Q. Yu, W. Donaldson, R. Sobolewski, P. Ampadu, “A study of effects of deflector position variation on leakage currents in ballistic deflection transistors,” in Proc. 2009 IEEE Nanotechnology Materials and Devices Conf., Traverse City, MI, June 2-5 2009.
  • Q. Yu and P. Ampadu, “Adaptive error control for NoC switch-to-switch links in a variable noise environment,” in Proc. 23rd IEEE Intl. Symp. on Defect and Fault Tolerance in VLSI Sys. (DFT’08), pp. 352-360, Oct. 2008.
  • Q. Yu and P. Ampadu, “Configurable error correction for multi-wire errors in switch-to-switch SoC links,” in Proc. 21st Annual IEEE Intl. SoC Conf. (SoCC’08), pp. 71-74, Sept. 2008.
  • Q. Yu and P. Ampadu, “Adaptive error control for reliable systems-on-chip,” in Proc. Intl. Symp. on Circuits and Syst. (ISCAS’08), pp. 832-835, May 2008.
Kingsbury Hall W215
33 Academic Way
Durham, NH 03824
Phone: 
(603) 862-1546
Fax: 
(603) 862-1832